BiCMOS noninverting buffer and logic gates

ABSTRACT

A BiCMOS logic circuit which implements single stage noninverting logic functions is described. The circuit includes pull-up and pull-down assembly means coupled between the input and output nodes. The pull-down assemby means comprises a pair of complimentary metal-oxide semiconductor field-effect transistors connected in an inverter configuration in which the gates of the pair of CMOS transistors are coupled to the input node while the output of the inverter configuration drives the base of a bipolar transistor coupled to the output node.

FIELD OF THE INVENTION

The present invention generally relates to the field of integrated circuits which combine bipolar and complimentary metal-oxide semiconductor (CMOS) devices on the same substrate.

BACKGROUND OF THE INVENTION

In recent years, much effort has been directed toward developing digital logic circuits which combine bipolar and CMOS technologies in a single integrated circuit. The marriage of bipolar and CMOS technologies is particularly advantageous since the superior aspects of each may be exploited and combined to yield optimal circuit performance.

For example, CMOS circuits have the advantages of extremely low quiescent power consumption, rail-to-rail output capability, high density and a very high input impedance. Bipolar logic circuits, on the other hand, are useful in driving large capactive loads, have fast switching capabilities and feature better performance over temperature and power supply. These attributes have led to the development of a family of BiCMOS inverting logic circuits which employ bipolar transistors to drive output loads, while utilizing CMOS devices to perform the basic logic functions.

BiCMOS inverter circuits, including the closely-related category of NAND logic gate circuits, are numerous and well-known in the prior art--so much so that their use dominates most digital logic designs. This reliance is so pervasive that, for instance, the conventional way of implementing a noninverting buffer is to connect two inverting buffers in series. In other words, noninverting logic circuits are essentially devoid in past designs.

In general, noninverting logic functions (e.g., OR gates) have been implemented in the past using inverting logic circuits (e.g., NOR gates) connected in series with an inverting buffer. The obvious disadvantage of such a configuration is the additional circuitry and greater complexity it requires. Furthermore, by including two logic gates between the input signal and output signal, the delay between a valid input transition and a valid output transition becomes about twice as long as the delay associated with a single stage device.

Another drawback of conventional BiCMOS logic circuitry is its need for high supply voltage during normal operation. This means that many prior art BiCMOS circuits do not operate well once the power supply voltage (e.g., V_(DD)) drops from its normal operating range (e.g., 5 volts). This latter characteristic is of particular concern since there is a growing momentum in the semiconductor industry to lower the standard operating supply potential from 5 volts to 3 volts in order to decrease the electric field to which the devices are subjected. When such a change is actually implemented, entire categories of BiCMOS logic circuits devices would no longer be feasible for use in this low operating supply environment.

Thus, what is needed is an integrated circuit combining CMOS and bipolar technologies which implements a noninverting buffer function in a single stage. Such a circuit should be capable of operating at a reduced supply potential. As will be seen, the present invention provides a noninverting BiCMOS buffer stage possessing these characteristics. In addition, the invented noninverting buffer stage is capable of being extended to give rise to an entirely new family of noninverting logic circuits. Adoption of the present invention promises to vastly reduce the complexity, while simultaneously increasing the speed and performance of modern digital integrated circuits fabricated using BiCMOS technology.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide a BiCMOS noninverting buffer circuit.

It is another object of the present invention to provide fast buffering of digital logic signals in a BiCMOS integrated circuit without inversion.

Yet another object of the present is to provide a BiCMOS logic circuit which implements single stage noninverting logic functions. A further object of the present invention is to provide a BiCMOS circuit which operates at low supply potentials.

Still another object of the present invention is to provide a BiCMOS circuit implementing single stage noninverting logic functions at a reduced transistor count.

It is another object of the present invention to provide a BiCMOS circuit having a reduced layout area and which provides an output voltage swing down to V_(ss).

Another object of the present invention is to provide a compact noninverting BiCMOS circuit capable of driving large capacitive loads.

In carrying out the above and other objects of the present invention in one form, there is disclosed a BiCMOS circuit comprising pull-up and pull-down assembly means coupled between input and output nodes. The pull-up assembly means is utilized for pulling the output node to a high logic state whenever a high logic potential is applied to the input node. Similarly, the pull-down assembly means drives the output node to a low logic state whenever a low logic potential is applied to the input node. The pull-down assembly means comprises a pair of complimentary metal-oxide semiconductor field-effect transistors connected in an inverter configuration in which the gates of the pair of CMOS transistors are coupled to the input node while the output of the inverter configuration drives the base of a bipolar transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and wherein:

FIG. 1 is a logic schematic of a prior art implementation of a noninverting buffer using two inverting buffers connected in series.

FIG. 2 is a circuit schematic of a typical prior art BiCMOS inverter.

FIG. 3 is a circuit schematic of the BiCMOS noninverting buffer stage of the present invention.

FIG. 4 is a logic diagram of a prior art implementation of a BiCMOS OR function.

FIG. 5 illustrates the BiCMOS circuit schematic of the present invention implementing the OR logic function in a single stage device.

FIG. 6 illustrates an alternative embodiment of the present invention implementing a BiCMOS noninverting buffer stage.

FIG. 7 illustrates a BiCMOS circuit implementation of a 2-input OR gate.

FIG. 8 is an alternative embodiment of the BiCMOS circuit of FIG. 6 for driving large capacitive loads.

FIG. 9 is an alternative embodiment of the BiCMOS circuit of FIG. 8 for driving large capactive loads.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

A BiCMOS noninverting buffer and logic gates are described. In the following description, numerous specific details are set forth, such as device types, voltages, etc., in order to provide a thorough understanding of the present invention. However, it will be obvious to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known elements have not been shown or described to avoid unnecessarily obscuring the present invention.

I. Discussion of the Prior Art

Before describing the present invention in detail, a basic understanding of conventional BiCMOS logic circuits will aid in appreciation of the details to follow.

With reference to FIG. 1, a logic diagram illustrating a past approach for implementing noninverting buffers in a BiCMOS circuit is illustrated. As previously described, noninverting BiCMOS buffers are conventionally implemented by connecting two inverting buffers 10 in series. Thus, application of the input logic signal "A" to the input of inverter 10 ultimately produces an output signal "A", shifted in time by the combined delays associated with both inverters.

FIG. 2 illustrates a schematic of a prior art inverter circuit 10. The circuit of FIG. 2 is described in connection with FIG. 5.3(A) in "BiCMOS Technology and Application", edited by Antonio R. Alvarez, Kluwer Academic Publishers, 1990. Inverter circuit 10 includes p-channel MOS (PMOS) transistor 12 and n-channel MOS (NMOS) transistors 14, 15 and 17. Also included are bipolar transistors 13 and 18 arranged in totem-pole fashion to provide a "push-pull" output drive function at node 21. PMOS device 12 is shown connected between the positive supply potential (V_(DD)) provided at node 11, and the base of NPN transistor 13. One terminal of NMOS device 14 is coupled to the base of NPN transistor 13 while the other terminal is coupled to V_(SS) (e.g., ground) at node 19. Transistor 17 is coupled across the base-emitter junction of NPN transistor 18. The gate of transistor 17 is coupled to the base of NPN transistor 13. NMOS device 15 is shown being coupled across the base-collector junction of NPN transistor 18. Each of field-effect transistors 12, 14 and 15 have their gate commonly connected to input node 20.

To explain the operation of BiCMOS inverter 10, consider first the effect of a logical low input (e.g., 0 volts) applied to input node 20. A low input voltage at node 20 causes PMOS device 12 to turn on, so that a highly conductive channel exists to source base current into pull-up transistor 13. NMOS devices 14 and 15, on the other hand are cut off; therefore, there is no D.C. path to supply base current to NPN transistor 18. Conversely, due to the high voltage potential at the base of transistor 13, NMOS device 17 will be on, thereby turning off the common emitter NPN transistor 18.

An analogus situation exists when a high voltage is placed on input node 20. For this situation, NMOS device 15 is able to provide base current to NPN transistor 18. This will discharge the load coupled to node 21 within a V_(BE) of ground. Note that PMOS device 12 is cut off; thus, NPN transistor 13 has no D.C. base current and is in fact kept off by NMOS device 14 pulling the base voltage low.

It is important to appreciate that the circuit of FIG. 2 has a logical low output voltage (V_(OL)) statically limited to a V_(BE) above ground. To begin the switching event, the input must exceed a potential equal to V_(BE+) V_(T). This creates a limitation on the minimum operating supply potential. Because the input will, in most instances, be driven by a previous inverter stage, the inverter of FIG. 2 actually requires a relatively high supply potential (e.g., 5 volts) which has sufficient head room (e.g., 2V_(BE's) +V_(T)) to maintain proper functionality. This constraint on supply voltage generally eliminates the BiCMOS inverter circuit of FIG. 2 from consideration in use in circuits employing a reduced power supply (i.e.,<5 volts).

FIG. 4 illustrates a standard prior art technique for implementing an OR operation using orthodox BiCMOS logic gates. The circuit schematic of FIG. 4 comprises NOR gate 35 coupled in series with inverter 10 to implement the logical sum of inputs "A" and "B" (i.e., A+B). Obviously, the main drawback of the logic circuit of FIG. 4 is the inclusion of a second inverter stage, along with its associated delay, in the signal path.

II. Discussion of the Present Invention

With reference to FIG. 3, there is shown the currently preferred embodiment of the BiCMOS noninverting buffer circuit 23 of the present invention. Buffer circuit 23 comprises pull-up assembly 25 and pull-down assembly 26. Pull-up assembly 25 includes an ordinary NPN bipolar transistor 28 configured as an emitter follower. The collector of transistor 28 is shown coupled to the positive supply potential V_(DD) (e.g., 3-5 volts), the base of transistor 28 is coupled to input node 31, and the emitter of transistor 28 is coupled to output node 32.

If input node 31 is taken to a high logical state (e.g., 5 volts) while the output voltage at node 32 is low (e.g., 0 volts), a high current will flow from the positive supply to the output, thereby pulling the voltage at output node 32 to a logical high level. Note that for this situation, current is supplied to the base of transistor 28 by the high voltage present at node 31. As will be described below, with input node 31 high, pull-down assembly 26 is inactive.

Pull-down assembly 26 includes p-channel MOS transistor 30 and n-channel MOS transistor 29, which are configured to resemble a CMOS inverter. In other words, PMOS device 30 and NMOS device 29 are connected in series between output node 32 and ground, with their gates being commonly tied to input node 31. The drains of NMOS device 29 and PMOS device 30 (i.e., the output of the CMOS inverter configuration) are both coupled to the base of NPN bipolar transistor 27. The emitter of transistor 27 is coupled to ground while the collector is coupled directly to output node 32. Together, bipolar transistors 28 and 27 are configured as a totem-pole output stage, with the source of PMOS device 30 being coupled to output node 32. Device 30 operates in a source follower mode with its output boosted by bipolar transistor 27.

Recognize that in a typical BiCMOS process, p-channel devices are fabricated within N-well regions (also referred to as bulk regions) formed in the semiconductor substrate. In many cases, the particular process flow mandates that these bulk regions be coupled directly to the positive supply potential, e.g.V_(CC). However, in processes which allow separate biasing of the bulk, it is preferred to couple the bulk of PMOS device 30 to output node 32. Doing so lowers the V_(T) of transistor 30 and eliminates the body effect resulting in an output which more closely tracks the input voltage.

To fully understand the operation of pull-down assembly 26, consider the case in which output node 32 is high and input node 31 transitions from a logical high to a logical low state. With input node 31 at a logical low voltage, PMOS device 30 becomes conductive so that current flows from output node 32 into the base of bipolar transistor 27, pulling it high. In response, NPN transistor 27 turns on, which pulls output node 32 down to a low potential.

Realize that in fabricating pull-down assembly 26, it is desirable to keep the basre capacitance of transistor 27 to a minimum. Keeping this capacitance small relative to the capacitance present at output node 32 eliminates charge sharing effects across PMOS device 30. These charge sharing effects might adversely influence the discharge rate at the output. Notwithstanding, even with charge sharing effects, the logical operation of pull-down assembly 26 remains the same; that is, a low voltage at input node 31 produces a low voltage at output node 32, and vis-a-versa.

For the situation where input node 31 is driven high, NMOS transistor 29 is turned on and PMOS device 30 is cut off. Turning on MOS transistor 29 discharges the base of bipolar transistor 27 to ground thereby turnig transistor 27 off. This allows output node 32 to be pulled high by the operation of pull-up assembly 25 as described above.

In circuit 23, the initiation of switching in the pull-down stage occurs when the input signal falls one p-channel MOSFET threshod below its source, which is connected to the output node 32. Initially, the output node is at or close to supply voltage V_(DD). This means that the drive on the base of bipolar transistor 27 is largely insensitive to the positive supply voltage V_(DD). Thus, the circuit retains its switching speed to low supply voltages (e.g., 3 volts). Buffer circuit 23 is, therefore, ideally suited for use in circuits having a low operating supply potential.

At first glance, the operation of circuit 23 may seem somewhat prosaic. However, practitioners in the art will appreciate the overall simplicity and advantages provided by circuit 23. In large part, these advantages are derived from the pull-down assembly configuration wherein a p-channel device is coupled across the collector-base junction of bipolar transistor 27, while an n-channel device 29 is coupled across the base-emitter junction of bipolar transistor 27. Effectively, PMOS device 30 functions as a psuedo or quasi-PNP emitter follower. Therefore, the pull-down assembly allows the present invention to operate as if it were a fully complimentary BiCMOS device, i.e., comprising both NMOS, PMOS and NPN, PNP transistors. (Normally, PNP transistors are eschewed in BiCMOS circuits because of the added complexity and difficulties they introduce into the fabrication sequence). Surprisingly, the composite circuit of FIG. 3 provides its noninverting logic operation utilizing only two bipolar transistors and two MOS transistors. This represents a minimum device count for a BiCMOS buffer stage. Moreover, only a single BiCMOS stage is present between the input and output nodes resulting in a shorter signal delay.

The basic concept presented in the circuit of FIG. 3 can be further extended to implement a variety of noninverting logic gates, such as an OR gate. These noninverting logic gates are implemented in the same manner as the noninverting buffer of circuit 23. By way of example, FIG. 5 is a circuit schematic of a two-input OR gate realized using standard BiCMOS technology. OR gate 40 comprises a pull-up assembly 41 and a pull-down assembly 45. Pull-up assembly 41 comprises a pair of NPN bipolar transistors 42 and 43 configured as emitter followers wherein each of transistors 42 and 43 have their emitters coupled to output node 51, their collectors coupled to positive supply line 52 (i.e., V_(DD)), and their respective bases coupled to input nodes 53 and 54.

The pull-down assembly of FIG. 5 includes a structure resembling a CMOS 2-input NOR driving the base of NPN bipolar transistor 46. The 2-input CMOS NOR structure comprises PMOS devices 47 and 48 connected in series between output node 51 and the base of transistor 46. NMOS devices 49 and 50 are coupled in parallel between the base of transistor 46 and ground node 53. The gates of devices 49 and 48 are commonly coupled to input node 54, while the gates of devices 47 and 50 are both coupled to input node 53. In accordance with the same principles described in connection with the noninverting buffer of FIG. 3, the PMOS devices in FIG. 5 are coupled across the collector-base junction of transistor 46 while the NMOS devices are coupled across the base-emitter junction of bipolar transistor 46.

The operation of the 2-input NOR gate of circuit 40 is similar to that of the noninverting buffer of FIG. 3. Output node 51 is pulled high if either input "A" (coupled to node 53) or input "B" (coupled to node 54) is raised to a high voltage, by virtue of the emitter configuration of pull-up assembly 41. Both transistors 42 and 43 are shut off if both "A" and "B" are low (e.g., 0 volts). When both inputs "A" and "B" are low, PMOS devices 47 and 48 are turned on. This provides a conductive path between output node 51 and the base of transistor 46. This pulls the base of transistor 46 high--turning it on to discharge the output voltage present at node 51. Note that when input nodes 53 and 54 are both low, MNOS devices 49 and 50 are off. If either input A or B is high, then one of the NMOS devices (either 49 or 50) will be turned on, thereby grounding the base of transistor 46. With its base grounded, transistor 46 is shut off and output node 51 is free to be pulled high by either of emitter followers 42 or 43.

The noninverting BiCMOS buffer of FIG. 3 can be expanded to form the BiNMOS non-inverting buffer 60 of FIG. 6. Basically, the difference between buffer 23 (FIG. 3) and buffer 60 (FIG. 6) is that transistor 27 is now replaced by NMOS device 62. Also, PMOS transistor 64 is now shown having its source coupled to the positive operating supply potential (e.g., V_(DD)) along line 67. The remainder of buffer 60 functions in a similar manner to that of buffer 23. Bipolar transistor 61 has its collector coupled to V_(DD), its base coupled to input node 66, and its emitter coupled to output node 63. Thus, NPN transistor 61 operates as a traditional emitter follower output.

Collectively, PMOS transistor 64 and NMOS transistor 65 operate as a traditional CMOS inverter with the gates of devices 64 and 65 being coupled to input node 66. The output of the CMOS configuration is coupled to the gate of NMOS transistor 62. Transistor 62 has its source coupled to V_(SS) (i.e., ground) and its drain coupled to output node 63.

During operation, when a high input is applied at node 66, PMOS device 64 is turned off and NMOS device 65 is on. This grounds the gate of device 62, turning it off. The high voltage at node 66 supplies base current to transistor 61 which, in turn, generates a logical high output voltage at node 63.

For the reverse situation in which a low voltage is applied to input node 66, transistors 61 and 65 are off. Conversely, PMOS device 64 is on (i.e., conductive) so that the supply potential V_(DD) is applied to the gate of NMOS device 62. This turns on device 62, thereby creating a conductive path between output node 63 and the supply potential V_(SS).

BiNMOS buffer 60 has the advantage of having an output voltage swing which extends completely down to V_(SS) (e.g., ground). In the circuit of FIG. 3, the logical low output voltage at node 32 only reaches within 0.2 volts to 0.6 volts of V_(SS) depending on the device sizes employed and the magnitude of the output capacitive load.

Furthermore, the circuit of FIG. 6 is advantageous in situations where layout area must be minimized. Since the layout area of a MOSFET is considerably smaller than that of a bipolar device, utilizing NMOS device 62 in place of an NPN bipolar transistor decreases the cell size considerably. It is appreciated by practitioners in the art that the speed degradation associated with buffer 60 is negligible when compared to buffer 23 of FIG. 3 for small output capacitive load applications. Of course, in cases in which a large output capacitance must be driven, buffer 23 may be preferred due to the full bipolar output stage. FIG. 8, to be discussed shortly, shows a BiNMOS buffer circuit capable of driving relatively large capacitive loads.

FIG. 7 illustrates a BiNMOS 2-input OR gate 70. The construction and operation of OR gate 70 is similar to that described in connection with the OR gate 40 of FIG. 5. The main difference lies in the fact that NPN bipolar transistor 46 has been replaced with NMOS device 72 in the output portion of the circuit. Also PMOS transistor 76 is shown having its source coupled to V_(DD) line 75 rather than to output node 73.

As before, the pull-up stage of gate 70 comprises NPN transistor 74 and 71 configured as emitter followers driving output node 73. The collectors of transistors 71 and 74 are coupled to supply line 75 while their bases are coupled to input nodes 82 and 81, respectively. Input node 81 is commonly coupled to the gates of PMOS transistor 77 and NMOS transistor 78. Input node 82 coupled to the gates of PMOS device 76 and NMOS device 79. Taken together, PMOS devices 76 and 77 and NMOS devices 78 and 79 collectively configured as a 2-input CMOS NOR structure whose output at node 80 is coupled to the gate NMOS device 72. Device 72 has its source coupled to V_(SS) and its drain connected to output node 73.

The operation of OR gate 70 is exactly analogous to that of the OR gate 40 of FIG. 5. That is, the voltage at output node 73 is pulled high if either input "A" (coupled to node 81) or input "B" (coupled to node 82) is raised to a high positive voltage by virtue of the emitter follower configuration of transistors 71 and 74. With a high voltage present at either of nodes 81 or 82, either of NMOS devices 78 or 79 are turned on, thereby coupling node 80 to V_(SS). This renders the channel region of device 72 non-conductive.

If both inputs "A" and "B" are low, PMOS devices 76 and 77 become conductive and NMOS devices 78 and 79 are turned off. This couples supply potential V_(DD) to node 80, which turns on NMOS device 72. Because of the low voltages on nodes 81 and 82, transistors 71 and 74 are turned off. Thus, with a high voltage present on node 80, NMOS device 72 becomes conductive and output node 73 is pulled down the supply potential V_(SS).

For the case in which the circuit of FIG. 6 is required to drive a large capacitive load, the alternative embodiment of FIG. 8 may be employed. The circuits of FIG. 6 and FIG. 8 have the same basic structure except that the output of the CMOS configuration comprising PMOS devices 64 and NMOS 65 now drive the base of NPN bipolar transistor 85. Transistor 85 has its collector coupled to the positive supply potential along line 67, and its emitter coupled to the gate of NMOS device 62. The noninverting buffer of FIG. 8 also includes an additional NMOS transistor 86 which has its source coupled to V_(SS), its drain coupled to the gate of NMOS device 62 and its gate coupled to input node 66. Note that for the situation in which a large capacitive load is coupled to output node 63, faster switching characteristics are obtained if NMOS device 62 has a large cross-sectional area. This allows it to handle relatively large current flows. Thus, transistor 85 becomes useful in driving the relatively large capacitance present at the gate of device 62.

The operation of the BiNMOS circuit of FIG. 8 is analogous to the circuit of FIG. 6. When a low voltage is applied at node 66, PMOS device 64 is turned on to flow current into the base of bipolar transistor 85. When a high input voltage is applied at node 66, NMOS device 86 is turned on, thereby grounding the gate of NMOS device 62. Thereafter, the output is pulled high by operation of bipolar transistor 61.

Similarly, the OR gate of FIG. 9 has an advantage over gate 70 of FIG. 7 for the case in which a large capacitive load is coupled to the output node. Again, the basic structure and operation of the circuit of FIG. 9 is identical to that of gate 70 except for the inclusion of an additional bipolar transistor and two n-channel devices. The pull-up stage comprises NPN bipolar transistors 91 and 92 configured as emitter followers coupled to output node 90. The collectors of transistors 91 and 92 are coupled to supply potential V_(DD) along line 101, and their bases are connected to input nodes 102 and 103, respectively. PMOS devices 95 and 96, and NMOS devices 97 and 98 comprise a 2-input CMOS NOR configuration having an output (i.e., node 104) which drives the base of NPN bipolar transistor 94. Transistor 94 and NMOS devices 99 and 100 are included to provide faster switching speed when output node 90 is coupled to a large capacitive load. In most cases, NMOS device 93, will have a large cross-sectional area in order to discharge large voltages rapidly.

When a high voltage is applied to either of input nodes 102 or 103, one of input devices 97 or 98 grounds the base of bipolar transistor 94, turning it off. Likewise, a high input turns on at least one of devices 99 or 100 to connect the gate of transistor 93 to V_(SS). Doing so turns transistor 93 off. Output node 90 can then be pulled high by either of devices 91 or 92.

When a low voltage potential is supplied to both of input nodes 102 and 103, PMOS devices 95 and 96 are both turned on. This supplies base current to NPN transistor 94, which then provides a high voltage to the gate of NMOS device 93. This turns on NMOS devices 93 so that a conductive path from node 90 to V_(SS) is established. Of course, with both inputs low transistors 91 and 92 are turned off. In this manner, the circuit of FIG. 9 implements a logical sum operation which is capable of driving large capacitive loads.

Thus, a BiCMOS noninverting buffer stage and logic gates have been described. 

We claim:
 1. A BiCMOS binary logic circuit implementing an OR function comprising:a plurality of emitter follower transistors, each having a base coupled to corresponding inputs of said circuit, said emitter follower transistors having their emitters commonly coupled to an output node; a pull-down circuit means including a plurality of complementary MOS transistors connected in a CMOS NOR configuration wherein the gates of pairs of said complementary MOS transistors are coupled to said corresponding inputs and the output of said NOR configuration is coupled to the base of a bipolar transistor, for sinking current from said output node through said bipolar transistor to pull the potential of said output node low when all of said inputs are driven with a low potential.
 2. The circuit of claim 1 wherein said bipolar transistor comprises an NPN transistor.
 3. The circuit of claim 2 wherein said circuit implements a two-input OR function and said plurality of complementary MOS transistors comprise a pair of p-channel MOS transistors coupled in series across the base-collector junction of said bipolar transistor and a pair of n-channel MOS transistors connected in parallel across the base-emitter junction of said bipolar transistor.
 4. A BiCMOS binary logic circuit implementing a logical sum operation comprising:a plurality of emitter follower transistors, each having a base coupled to corresponding inputs, said emitter follower transistors having their emitters commonly coupled to an output node; a pull-down circuit means including a plurality of complementary MOS transistors connected in a CMOS NOR configuration, wherein gates of pairs of said complementary MOS transistors are coupled to said corresponding inputs and the output of said NOR configuration is coupled to the gate of an NMOS transistor, for sinking current from said output node through said NMOS transistor to pull the potential of said output node low when all of said inputs are driven with a low potential.
 5. The circuit of claim 4 wherein said plurality of complementary MOS transistors comprise a pair of p-channel MOS transistors coupled in series between a first supply potential and the gate of said NMOS transistor, and a pair of n-channel MOS transistors connected in parallel between the gate of said NMOS transistor and a second supply potential.
 6. The circuit of claim 5 wherein said first supply potential comprises a high positive potential and said second supply potential comprises ground.
 7. The circuit of claim 5 wherein the output of said NOR configuration is coupled to the base of a bipolar transistor having its emitter coupled to the gate of said NMOS transistor and its collector coupled to said first supply potential, said bipolar transistor providing faster switching when said circuit draws relatively large capacitive loads.
 8. The circuit of claim 7 further comprising another pair of n-channel MOS transistors connected in parallel between the emitter of said bipolar transistor and said second supply potential, the gates of said another pair of n-channel MOS transistors being coupled to said corresponding inputs.
 9. The circuit of claim 8 wherein said first supply potential comprises a high positive potential in said second supply potential comprises ground. 